Design a Digital Phase Detector for Clock Synchronization in MPSOC

Faiq Khalid Lodhi , Naeha Sharif, Nadra Ramzan, Syed Rafay Hasan and Osman Hasan


This project intends to provide a safe solution for crossing data between multiple clock domains of an MPSoC while satisfying the timing constraints. The exotic solution consists of a Digital Phase Detector (DPD) that not only estimates phase variations between clock domains but also synchronizes them simultaneously.

The proposed design of the DPD has three modules. First module is D-Flip Flop bank which samples the incoming control/clock signal based on a definite sampling criterion. The second module (Decision maker) analyzes the sampled information, resolves the phase of the incoming clock and passes this information to the third module. The third module (Selection block) uses this information to output the clock phase most in synch with the incoming one. The novel design is applicable to systems on chip requiring phase detection and synchronization and is implemented using Cadence tools (90nm technology). The results obtained prove it to be a low latency, low power and efficient design.



Block diagram of mesochronous synchronizer


Block diagram of proposed Digital Phase Detector


  1. F. K. Lodhi, N. Sharif, N. Ramzan, O. Hasan and S. R. Hasan, “Timing variation aware dynamic digital phase detector for low-latency clock domain crossing”, IET Circuits, Devices & Systems, vol.8, no.1, pp. 58 – 64, Jan. 2014.

  2. F. K. Lodhi, N. Sharif, N. Ramzan, O. Hasan and S. R. Hasan, ” Quantitative Analysis of State-of-the-Art Synchronizers: Clock Domain Crossing Perspective, ” IEEE International Conference on Emerging Technologies (ICET-11), Islamabad, Pakistan, September 2011, pp. 1 – 6.