Engr. Faiq Khalid

• Introduction
• Biography
• Research
• Publications
• Contact

• I am the Project Assistant at ​at the Research Group for Computer Architecture and Robust, Energy-Efficient Technologies (CARE-Tech.), Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria, under the supervision of Dr. Muhammad Shafique.​​ Previously, I was the Research Assistant at System Analysis and Verification (SAVe) Lab of School of Electrical Engineering and Computer Sciences, National University of Sciences and Technology under the supervision of Dr. Osman Hasan . My main research interests include formal analysis and verification of embedded systems, hardware design security, design reliability of VLSI circuits.

  Currently, I am working on Cross-Layer Reliability and Security for Multi-Processor Systems-on-Chip (MPSoC). The aim of this research work is to provide a generic methodology to design and implement the run-time solutions to estimate the vulnerabilities and to detect the malicious intrusions and cyber/hardware attacks on different layers of MPSoC.

  Moreover, I am pursuing my PhD Degree in hardware security at Vienna University of Technology (TU Wien), Austria. I am also doing my research work as a part of DAAD Deutsch-Pakistanische Forschungskooperationen Project: “Formal Verification of Distributed Thermal and Resource Management Schemes for On-Chip Many-Core Systems”. The aim of this research work is to illustrate the practical effectiveness of model checking by applying it to accurately analyze and improve upon some of the recently developed and widely used distributed DTM and DRM algorithms for on-chip many-core systems. As a part of the above-mentioned project, I went for a research internships from 16th April 2016 to 4th May 2016 and 5th December 2016 to 30th December 2016 at Chair for Embedded Systems (CES) under the supervision of Prof. Dr. Joerg Henkel in Karlsruhe Institute of Technology (KIT).

• Biography

  Faiq Khalid received the MS Electrical Engineering and BE Electronics Engineering degrees from National University of Sciences and Technology (NUST), Pakistan in 2016 and 2011, respectively. Currently, Mr. Khalid is pursuing my PhD Degree in hardware security at Vienna University of Technology (TU Wien), Austria. Since May 2017, he is working as a Project Assistant at ​at the Research Group for Computer Architecture and Robust, Energy-Efficient Technologies (CARE-Tech.), Institute of Computer Engineering, Vienna University of Technology (TU Wien), Austria, under the supervision of Dr. Muhammad Shafique.​​ Mr. Khalid has also worked as Research Assistant in System Analysis and Verification (SAVe) Lab at NUST School of Electrical Engineering and Computer Sciences. Mr. Khalid has won the Quid-e-Azam gold medal for his academics achievements and best researcher at SAVe Lab for 2014. His research interests include formal analysis and verification of embedded systems, hardware design security, design reliability of VLSI circuits. Mr. Khalid is a member of Pakistan engineering council.

• Hardware Security

  1. Run-time Hardware Trojan Monitors through modeling Burst Mode Communication
  2. A Self-learning Framework to Detect the Intruded Integrated Circuits
  3. Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification
  4. Hardware Trojan detection in SE Tolerant Macro Synchronous Micro Asynchronous (MSMA) pipeline

  Model Checking

  1. Formal Verification of Gate-Level Multiple Side Channel Parameters to detect Hardware Trojans
  2. Formal Analysis of Macro Synchronous Micro Asychronous Pipeline for Hardware Trojan Detection
  3. CAnDy-TM: Comparative Analysis of Central & Distributed DTM in Many-Cores using Model Checking
  4. FAMe-TM: Formal Analysis Methodology for Task Migration Algorithms in Many-Core Systems
  5. Formal Verification of DTM for Thermal Management in On-chip Multi-core Systems using nuXmv

  Digital VLSI Design

  1. Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline
  2. Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase
  3. Design of A Digital Phase Detector for Clock Synchronization in MPSoC
  4. Towards Precise, Scalable and Automatic Analysis of Analog and
     

• Refereed Journals

  1. S. A. A. Bukhari, F. K. Lodhi, O. Hasan, M. Shafique and J. Henkel, “FAMe-TM: Formal Analysis Methodology for Task Migration Algorithms in Many-Core Systems”, Science of Computer Programming, Elsevier, Vol. 133, Part 2, 2017, pp. 154-174.

  2. F. K. Lodhi, S. R. Hasan, O. Hasan, and F. Awwad, “Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification”, Journal of Electronic Testing: Theory and Applications, Volume 32, Issue 5, Springer 2016.

  3. F. K. Lodhi, N. Sharif, N. Ramzan, O. Hasan and S. R. Hasan, “Timing variation aware dynamic digital phase detector for low-latency clock domain crossing”, IET Circuits, Devices & Systems, Volume 8, Issue 1, pp. 58 – 64, Jan. 2014.

  Peer Reviewed Conferences

  1. F. Khalid, S. R. Hasan, O. Hasan and F. Awwad, “Behavior Profiling of Power Distribution Networks for Runtime Hardware Trojan Detection”, International Midwest Symposium on Circuits and Systems (MWSCAS 2017), IEEE Circuit and System Society (CAS), Boston, MA, USA, To Appear.

  2. F. K. Lodhi, O. Hasan, S. R. Hasan and F. Awwad, “Power Profiling of Instructions of Microcontroller to Detect Hardware Trojans without Golden Circuit Models”, Design, Automation and Test in Europe (DATE-2017), Swisstech, Laussane, Switzerland, pp. 294 – 297.

  3. S. A. A. Bukhari, F. K. Lodhi, O. Hasan, M. Shafique and J. Henkel, “CAnDy-TM: Comparative Analysis of Dynamic Thermal Management in Many-Cores using Model Checking”, Design, Automation and Test in Europe (DATE-2017), Swisstech, Laussane, Switzerland, pp. 1289 – 1292

  4. I. Abbasi, F. K. Lodhi, A. Kamboh, O. Hasan, “Formal Verification of Gate-Level Multiple Side Channel Parameters to detect Hardware Trojans“, Fifth International Workshop on Formal Techniques for Safety-Critical Systems (FTSCS 2016), Tokyo, Japan, pp. 75-92.

  5. W. Gul, S. R. Hasan and O. Hasan, F. K. Lodhi and F. Awwad,”Synchronously Triggered GALS Design Templates Leveraging QDI Asynchronous Interfaces“, in IEEE Symposium on circuits and System (ISCAS 2016), Montreal, QC, 2016, pp. 2615-2618.

  6. F. K. Lodhi, I. Abbasi, F. Khalid, O. Hasan, S. R. Hasan and F. Awwad,”A Self-Learning Framework to Detect the Intruded Integrated Circuits“, in IEEE Symposium on circuits and System (ISCAS 2016), Montreal, QC, 2016, pp. 1702-1705.

  7. F. K. Lodhi, O. Hasan, S. R. Hasan and F. Awwad,”Formal Analysis of Macro Synchronous Micro Asychronous Pipeline for Hardware Trojan Detection, ” in Nordic Circuits and Systems Conference (NORCAS 2015): NORCHIP & International Symposium on System-on-Chip (SoC), Oct. 2015, pp.1-4.

  8. S. A. A. Bukhari, F. K. Lodhi, O. Hasan, M. Shafique and J. Henkel, “Formal Verification of Distributed Task Migration for Thermal Management in On-chip Multi-core Systems using nuXmv”, Third International Workshop on Formal Techniques for Safety-Critical Systems (FTSCS 2014), Luxembourg City, Luxembourg, 2014, pp 32-46.

  9. F. K. Lodhi, O. Hasan, S. R. Hasan and F. Awwad,”Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline, ” in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), IEEE Circuit and System Society (CAS), Aug. 2014, pp. 659 – 662.

  10. F. K. Lodhi, O. Hasan, S. R. Hasan and F. Awwad, “Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014), July 2014, pp. 601 – 606.

  11. F. K. Lodhi, O. Hasan, S. R. Hasan and F. Awwad, “Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase, ” in IEEE International Midwest Symposium on Circuits and Systems (MWCAS 2012) ,IEEE Circuit and System Society (CAS), Boise, Iadho, USA, pp. 402 – 405.

  12. N. Sharif, N. Ramzan, F. K. Lodhi, O. Hasan and S. R. Hasan, ” Quantitative Analysis of State-of-the-Art Synchronizers: Clock Domain Crossing Perspective, ” IEEE International Conference on Emerging Technologies (ICET-11), Islamabad, Pakistan, September 2011, pp. 1 – 6.

  13. F. K. Lodhi, N. Ramzan and O. Hasan, , “Towards Precise, Scalable and Automatic Analysis of Analog and Mixed Signal Circuits“, IEEE International Conference on Information and Emerging Technologies (ICIET-10), Karachi, Pakistan, June 2010, pp 1-6.

  Book Chapters

  1. I. Abbasi, F. K. Lodhi, A. Kamboh, O. Hasan, “Formal Verification of Gate-Level Multiple Side Channel Parameters to detect Hardware Trojans“, Fifth International Workshop on Formal Techniques for Safety-Critical Systems, 2016, pp 75-92.

  2. S. A. A. Bukhari, F. K. Lodhi, O. Hasan, M. Shafique and J. Henkel, “Formal Verification of Distributed Task Migration for Thermal Management in On-chip Multi-core Systems using nuXmv”, Formal Techniques for Safety-Critical Systems, 2014, pp 32-46.

  Technical Report

  1. S.A.A. Bukhari, F. K. Lodhi and O. Hasan, “Formal Verification of Distributed Task Migration for Thermal Management in On-chip Multi-core Systems using nuXmv”, Technical Report, NUST, Islamabad, Pakistan, 2014.

  Masters Thesis

  1. F. K. Lodhi, “Runtime Hardware Trojan Monitors through modeling Burst Mode Communication”, Masters Thesis, National University of Sciences and Technology (NUST), Islamabad, Pakistan. 2016.

• Contact Details	Address
  Current: Project Assistantat at CARE-Tech Research Lab Previous: Research Assistantat at SAVe Lab Email: faiq.khalid@tuwien.ac.at Email: faiq.khalid@seecs.edu.pk Cell: +43-664-9585277	​CARE-Tech Research Lab ​Embedded Computing Systems Group Institute of Computer Engineering Vienna University of Technology Treitlstrasse 3, 2nd floor, 1040 Wien, Austria

   
  

  
   

Current: Project Assistant in ​CARE-Tech Research Lab at ​Embedded Computing Systems Group, Institute of Computer Engineering, Vienna University of Technology

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