Formal methods are being increasingly advocated these days to validate and verify systems used in safety-critical domains, such as healthcare, transportation and power generation and distribution. Formal analysis of a system requires a deep understanding of the system besides the know how of formal validation and verification techniques. The aim of this workshop is to bridge the gap between the SEECS students and faculty members, who are working with formal methods, and the engineers who are interested in investigating the usage of formal methods for improving the accuracy and reliability of their safety-critical designs or systems.
In the third event of this series, the team members of the System Analysis and Verification (SAVe) Lab will share brief overviews of their research work related to the area of hardware design, particularly ASIC Design, with the attendees of the workshop.
The workshop will provide a forum for discussions and the exchange of innovative ideas and thus is expected to lead to future collaborative projects. It would provide the opportunity of exploring the available research directions at the SAVe Lab to the graduate students, who are looking for research topics. Moreover, the research students of SAVe lab hope to receive some positive feedback on their research projects from the SEECS community as well.
Please register before 12 noon on Thursday (December 1, 2016) by using the registration tab. The registration is free but is mandatory for attending.
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06:00pm to 08:00pm
Seminar Hall, PG Block, NUST SEECS
Friday, 2nd December 2016 (6:00 – 8:00 pm)
Timestamp Name Topic of the Presentation 6:00 – 6:15 PM Osman Hasan Welcome Note 6:15 – 6:25 PM Faiq Khalid Lodhi Introduction to VLSI Design 6:25 – 6:30 PM Sunil Najiani Introduction to Clock Multiplier 6:30 – 6:40 PM Muhammad Usama Sardar Introduction to Thermal Management in Multi-core Systems 6:40 – 6:45 PM Mishal Minhas Validation of Digital Circuits 6:45 – 6:50 PM Quart-ul-Ain Timing Analysis of digital circuits 6:50 – 6:55 PM Shahid Ali Murtza Vertgen: Verilog Testbench Generator 6:55 – 7:00 PM Rashid Khalid Lodhi Automatic Software Testing 7:00 – 7:05 PM Adnan Rashid Using Transform Methods for Analyzing the Safety Critical Systems 7:05 – 7:10 PM Asad Ahmed Accurate Analysis of Power Electronics 7:10 – 7:15 PM Abid Rauf Analyzing the Security Applications 7:15 – 7:45 PM TEA BREAK
General Program Chair
System Analysis & Verification (SAVe) Lab
School of Electrical Engineering and Computer Sciences (SEECS)
National University of Science & Technology (NUST)
Sector H-12, Islamabad, 44000, Pakistan